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wiRedPanda
Logic Circuit Simulator
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This is the complete list of members for MappedPinSystemVerilog, including all inherited members.
| m_elm | MappedPinSystemVerilog | |
| m_pin | MappedPinSystemVerilog | |
| m_port | MappedPinSystemVerilog | |
| m_portNumber | MappedPinSystemVerilog | |
| m_varName | MappedPinSystemVerilog | |
| MappedPinSystemVerilog()=default | MappedPinSystemVerilog | |
| MappedPinSystemVerilog(GraphicElement *elm, const QString &pin, const QString &varName, Port *port, const int portNumber=0) | MappedPinSystemVerilog | inline |