Maps a circuit port to its generated SystemVerilog signal name and module port. More...

Public Member Functions
	MappedPinSystemVerilog ()=default
	MappedPinSystemVerilog (GraphicElement elm, const QString &pin, const QString &varName, Port port, const int portNumber=0)
	Constructs a pin mapping.

Public Attributes
GraphicElement *	m_elm = nullptr
	Owning graphic element.
QString	m_pin
	Top-level module port name.
Port *	m_port = nullptr
	Source port in the circuit graph.
int	m_portNumber = 0
	Port index within the element.
QString	m_varName
	Generated internal signal name.

Detailed Description

Maps a circuit port to its generated SystemVerilog signal name and module port.

Definition at line 30 of file SystemVerilogCodeGen.h.

Constructor & Destructor Documentation

MappedPinSystemVerilog::MappedPinSystemVerilog ( )

default

MappedPinSystemVerilog::MappedPinSystemVerilog	(	GraphicElement *	elm,
		const QString &	pin,
		const QString &	varName,
		Port *	port,
		const int	portNumber = 0 )

inline

Constructs a pin mapping.

Parameters

elm	Owning graphic element.
pin	Top-level module port name.
varName	Internal signal/wire name in the generated code.
port	Source Port this mapping refers to.
portNumber	Index of the port within the element (default 0).