wiRedPanda
Logic Circuit Simulator
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SystemVerilogCodeGen.cpp File Reference
#include "App/CodeGen/SystemVerilogCodeGen.h"
#include <QFileInfo>
#include <QRegularExpression>
#include <QSet>
#include "App/CodeGen/CodeGenUtils.h"
#include "App/Core/Common.h"
#include "App/Element/GraphicElement.h"
#include "App/Element/GraphicElements/Clock.h"
#include "App/Element/GraphicElements/TruthTable.h"
#include "App/Element/IC.h"
#include "App/Scene/Scene.h"
#include "App/Wiring/Connection.h"
#include "App/Wiring/Port.h"
Include dependency graph for SystemVerilogCodeGen.cpp:

Go to the source code of this file.

Functions

static QString icModuleKey (const IC *ic)
static bool isSystemVerilogReserved (const QString &name)

Function Documentation

◆ icModuleKey()

QString icModuleKey ( const IC * ic)
static

Returns a unique key identifying an IC for SystemVerilog code generation. Embedded ICs use "embedded:blobName"; file-backed ICs use their canonical file path.

Definition at line 22 of file SystemVerilogCodeGen.cpp.

References IC::blobName(), IC::file(), and IC::isEmbedded().

◆ isSystemVerilogReserved()

bool isSystemVerilogReserved ( const QString & name)
static

Definition at line 169 of file SystemVerilogCodeGen.cpp.