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wiRedPanda
Logic Circuit Simulator
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#include "App/CodeGen/SystemVerilogCodeGen.h"#include <QFileInfo>#include <QRegularExpression>#include <QSet>#include "App/CodeGen/CodeGenUtils.h"#include "App/Core/Common.h"#include "App/Element/GraphicElement.h"#include "App/Element/GraphicElements/Clock.h"#include "App/Element/GraphicElements/TruthTable.h"#include "App/Element/IC.h"#include "App/Scene/Scene.h"#include "App/Wiring/Connection.h"#include "App/Wiring/Port.h"Go to the source code of this file.
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| static QString | icModuleKey (const IC *ic) |
| static bool | isSystemVerilogReserved (const QString &name) |
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Returns a unique key identifying an IC for SystemVerilog code generation. Embedded ICs use "embedded:blobName"; file-backed ICs use their canonical file path.
Definition at line 22 of file SystemVerilogCodeGen.cpp.
References IC::blobName(), IC::file(), and IC::isEmbedded().
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Definition at line 169 of file SystemVerilogCodeGen.cpp.