SystemVerilogCodeGen.h

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// Copyright 2015 - 2026, GIBIS-UNIFESP and the wiRedPanda contributors
// SPDX-License-Identifier: GPL-3.0-or-later

 
#pragma once
 
#include <functional>
 
#include <QCoreApplication>
#include <QFile>
#include <QHash>
#include <QSet>
#include <QTextStream>
#include <QVector>
 
#include "App/Core/Enums.h"
 
class GraphicElement;
class IC;
class InputPort;
class Port;

class MappedPinSystemVerilog
{
public:
    MappedPinSystemVerilog() = default;
    MappedPinSystemVerilog(GraphicElement *elm, const QString &pin, const QString &varName, Port *port, const int portNumber = 0)
        : m_elm(elm)
        , m_port(port)
        , m_pin(pin)
        , m_varName(varName)
        , m_portNumber(portNumber)
    {
    }
 
    GraphicElement *m_elm = nullptr; 
    Port *m_port = nullptr;       
    QString m_pin;                   
    QString m_varName;               
    int m_portNumber = 0;            
};

struct ICModuleInfo {
    QString moduleName;                        
    QString sourceFile;                        
    QVector<QString> inputNames;               
    QVector<QString> outputNames;              
    IC *prototypeIC = nullptr;                 
    bool generated = false;                    
};

class SystemVerilogCodeGen
{
    Q_DECLARE_TR_FUNCTIONS(SystemVerilogCodeGen)
 
public:
    SystemVerilogCodeGen(const QString &fileName, const QVector<GraphicElement *> &elements);

    void generate();

    const QVector<MappedPinSystemVerilog> &inputMap() const { return m_inputMap; }
    const QVector<MappedPinSystemVerilog> &outputMap() const { return m_outputMap; }
    const QString &moduleName() const { return m_fileName; }
 
private:
    // --- String Utilities ---

    static QString highLow(Status val);

    static QString fourState(Status val);
    static QString removeForbiddenChars(const QString &input);
    static bool isSimpleIdentifier(const QString &expr);
 
    // --- Signal Name Resolution ---

    QString otherPortName(Port *port);
    QString otherPortNameImpl(Port *port, QSet<Port *> &visited);
    QString ensureSimpleSignal(const QString &expr);
 
    // --- Variable / Declaration Emission ---

    void assignVariablesRec(const QVector<GraphicElement *> &elements);
    void collectICTypes(const QVector<GraphicElement *> &elements);
    void declareAuxVariables();
    void declareAuxVariablesRec(const QVector<GraphicElement *> &elements);
    void declareInputs();
    void declareOutputs();
 
    // --- Sequential Logic Emission ---

    void emitSequentialBlock(const QString &typeName,
                             const QString &clk, const QString &rawPrst, const QString &rawClr,
                             const std::function<void()> &emitPresetBody,
                             const std::function<void()> &emitClearBody,
                             const std::function<void()> &emitNormalBody);
 
    // --- IC Module Generation ---

    void generateICModules();
    void generateSingleICModule(ICModuleInfo &info);
    static QSet<GraphicElement *> findFeedbackElements(const QVector<GraphicElement *> &elements);
 
    // --- Combinational Logic ---

    QString generateLogicExpression(GraphicElement *elm);
    QString generateLogicExpressionImpl(GraphicElement *elm, QSet<Port *> &visited);
 
    // --- Top-Level Structure ---

    void loop();
 
    // --- Members ---
 
    QFile m_file;                              
    QHash<Port *, QString> m_varMap;        
    QHash<QString, InputPort *> m_txInputPorts; 
    QHash<QString, ICModuleInfo> m_icModules;  
    QHash<IC *, QString> m_instanceNames;      
    QStringList m_availablePins;               
    QString m_fileName;                        
    QTextStream m_stream;                      
    QVector<MappedPinSystemVerilog> m_inputMap; 
    QVector<MappedPinSystemVerilog> m_outputMap; 
    const QVector<GraphicElement *> m_elements; 
    bool m_generatingICModule = false;         
    int m_globalCounter = 1;                   
    QSet<GraphicElement *> m_feedbackElements; 
};