ICModuleInfo Struct Reference

Metadata for a single IC module during SystemVerilog hierarchical generation. More...

#include <SystemVerilogCodeGen.h>

Public Attributes
bool	generated = false
	True once the module body has been emitted.
QVector< QString >	inputNames
	Port names for the module's inputs.
QString	moduleName
	Generated module identifier.
QVector< QString >	outputNames
	Port names for the module's outputs.
IC *	prototypeIC = nullptr
	Representative IC element (used to inspect sub-circuit).
QString	sourceFile
	Original .panda file path (or blob name).

Detailed Description

Metadata for a single IC module during SystemVerilog hierarchical generation.

Definition at line 62 of file SystemVerilogCodeGen.h.

Member Data Documentation

generated

bool ICModuleInfo::generated = false

True once the module body has been emitted.

Definition at line 68 of file SystemVerilogCodeGen.h.

inputNames

QVector<QString> ICModuleInfo::inputNames

Port names for the module's inputs.

Definition at line 65 of file SystemVerilogCodeGen.h.

moduleName

QString ICModuleInfo::moduleName

Generated module identifier.

Definition at line 63 of file SystemVerilogCodeGen.h.

outputNames

QVector<QString> ICModuleInfo::outputNames

Port names for the module's outputs.

Definition at line 66 of file SystemVerilogCodeGen.h.

prototypeIC

IC* ICModuleInfo::prototypeIC = nullptr

Representative IC element (used to inspect sub-circuit).

Definition at line 67 of file SystemVerilogCodeGen.h.

sourceFile

QString ICModuleInfo::sourceFile

Original .panda file path (or blob name).

Definition at line 64 of file SystemVerilogCodeGen.h.

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The documentation for this struct was generated from the following file:

• SystemVerilogCodeGen.h