SystemVerilogCodeGen Class Reference

Generates a synthesisable SystemVerilog module from a circuit's element graph. More...

#include <SystemVerilogCodeGen.h>

Public Member Functions
void	generate ()
	Generates the SystemVerilog output file for the circuit.
const QVector< MappedPinSystemVerilog > &	inputMap () const
	Returns the mapped input pins after generation.
const QString &	moduleName () const
	Returns the top-level module name derived from the file name.
const QVector< MappedPinSystemVerilog > &	outputMap () const
	Returns the mapped output pins after generation.
	SystemVerilogCodeGen (const QString &fileName, const QVector< GraphicElement * > &elements)
	Constructs the code generator for the given output fileName and circuit elements.

Detailed Description

Generates a synthesisable SystemVerilog module from a circuit's element graph.

Walks the topologically sorted element list, maps each gate/flip-flop to SystemVerilog constructs, and handles hierarchical IC modules by recursively generating sub-modules. Wireless Tx/Rx nodes are resolved via the same label-matching used by the simulation engine.

Definition at line 80 of file SystemVerilogCodeGen.h.

Constructor & Destructor Documentation

SystemVerilogCodeGen()

SystemVerilogCodeGen::SystemVerilogCodeGen	(	const QString &	fileName,
		const QVector< GraphicElement * > &	elements )

Constructs the code generator for the given output fileName and circuit elements.

Definition at line 31 of file SystemVerilogCodeGen.cpp.

Member Function Documentation

generate()

void SystemVerilogCodeGen::generate

(

)

Generates the SystemVerilog output file for the circuit.

Definition at line 491 of file SystemVerilogCodeGen.cpp.

References Scene::wirelessTxInputPorts().

Referenced by ExportController::exportToSystemVerilog().

inputMap()

const QVector< MappedPinSystemVerilog > & SystemVerilogCodeGen::inputMap ( ) const

inline

Returns the mapped input pins after generation.

Definition at line 92 of file SystemVerilogCodeGen.h.

moduleName()

const QString & SystemVerilogCodeGen::moduleName ( ) const

inline

Returns the top-level module name derived from the file name.

Definition at line 96 of file SystemVerilogCodeGen.h.

outputMap()

const QVector< MappedPinSystemVerilog > & SystemVerilogCodeGen::outputMap ( ) const

inline

Returns the mapped output pins after generation.

Definition at line 94 of file SystemVerilogCodeGen.h.

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The documentation for this class was generated from the following files:

• SystemVerilogCodeGen.h
• SystemVerilogCodeGen.cpp