SystemVerilogCodeGen.h File Reference

SystemVerilog code generator: translates a circuit into a synthesisable module. More...

#include <functional>
#include <QCoreApplication>
#include <QFile>
#include <QHash>
#include <QSet>
#include <QTextStream>
#include <QVector>
#include "App/Core/Enums.h"

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Classes
struct	ICModuleInfo
	Metadata for a single IC module during SystemVerilog hierarchical generation. More...
class	MappedPinSystemVerilog
	Maps a circuit port to its generated SystemVerilog signal name and module port. More...
class	SystemVerilogCodeGen
	Generates a synthesisable SystemVerilog module from a circuit's element graph. More...

Detailed Description

SystemVerilog code generator: translates a circuit into a synthesisable module.

Definition in file SystemVerilogCodeGen.h.